Our Team has expertise in
Developing verification testbench components for chip/module level using System Verilog, C/C++
Verification methodologies (Object oriented, UVM etc) to develop extendable test-bench/test-cases environment.
Defining and executing detailed verification plan from spec working with architects, designers, system engineers.
Writing tests, Debugging tests, automating regression scripts and regression environment.
Incorporating code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tapeout.