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Physical Design

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Our Physical Design team has together taped out more than 70 ASICs targeted to various fabs such as TSMC, Global Foundries, IBM, TI, Towerjazz in process nodes 130nm, 90nm, 65nm, 40/45nm, 32nm, 28nm, 22nm, 16nm finfet, 14nm finfet. The team has expertise in
Timing Constraints Preparation and Validation
Logic/Physical Synthesis
Full chip partitioning
IO ring preparation
Placement
Clock Tree Synthesis
Timing Closure
SI Analysis and Repair
IR drop Analysis and Repair
Static Timing Analysis
Physical Verification
EDA tools from Cadence, Synopsys, Mentor, Apache
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