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Current Openings

Physical Design Engineers
Primary Responsibilities and Requirements.

    BE/B.Tech /ME/M.Tech 3 years to 15 years.

  • He/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.
  • Provide technical guidance, mentoring to physical design engrs.
  • Interface with front-end ASIC teams to resolve issues.
  • Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques.
  • Timing closure on DDR2/DDR3/PCIE interfaces.
  • Excellent communication skills.
  • Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
  • Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.
  • Expertise in scripting languages such as PERL, TCL.
  • Strong Physical Verification skill set.
  • Static Timing Analysis in Primetime or Primetime-SI.
  • Good written and oral communication skills. Ability to clearly document plans.
  • Ability to interface with different teams and prioritize work based on project needs.
Email id: jobs@firstpass-semi.com
Analog Layout Engineers.
Primary Responsibilities and Requirements.

    BE/B.Tech /ME/M.Tech 3 years to 15 years

  • He/She should be able to act as focal point with customers, work and lead a team of 3-4 custom layout engineers on analog layout, physical verification, maintaining PDKs, ealuating them. The candidates should have a strong expertise in some critical layouts such as PLL, DLL, LNA, VGA, ADC, LDO. He/She should be able to adapt to new technologies/tools/flows pretty quickly.
  • Expertise in Custom Layout Standard Cells, I/O or special analog designs such as RF transceivers, LNA, VGA, PLL, DLL, LDO, Bandgap, VCO, ADC,DAC.
  • Strong Layout Design Concepts.
  • Experience in Pcell development, maintaining and modifying PDKs.
  • Experience in Layout Design tools such as Virtuoso, Virtuoso-XL.
  • Expertise in SKILL Programming Language.
  • Experience in Physical verification.
  • Exposure to Calibre, Hercules and Assura.
  • Exposure to digital place & route.
  • Should be able to mentor layout engineers and act as focal point with customers.
  • Good understanding of Analog Design.
  • Strong basics in process technology, fabrication techniques.
  • Good written and oral communication skills. Ability to clearly document plans.
  • Ability to interface with different teams and prioritize work based on project needs.
Email id: jobs@firstpass-semi.com
Design & Verification Engineers.
Primary Responsibilities and Requirements.

    BE/B.Tech /ME/M.Tech 2 years to 15 years

  • Develop verification testbench components for chip/module level using System Verilog, C/C++.
  • Use Verification methodologies (Object oriented, UVM etc) to develop extendable test-bench/test-cases environment.
  • Define and execute detailed verification plan from spec working with architects, designers, system engineers.
  • Write tests, Debug tests, automate regression scripts and regression environment.
  • Incorporate code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tapeout.
  • Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required.
  • Excellent debugging skills in both SW and ASIC hardware.
  • Must be good in building verification environments preferably using Verilog, System Verilog, UVM, C/C++/PLI etc.
  • Proficiency in scripting language like Perl, Tcl/Tk, Shell is a definite plus.
  • Experience with simulators like ncVerilog (Incisive), VCS, Eldo and debug tools like Verdi/Debussy.
  • Good understanding of latest formal verification techniques, assertions, properties is a plus.
  • Understanding or prior experience with Industry standard protocols like USB, SPI, SATA, Ethernet, DisplayPort, SRIO etc is a definite plus.
  • Understanding or Prior Experience in ARM/Tensillica Processor platforms is a definite plus.
  • Good written and oral communication skills. Ability to clearly document plans.
  • bility to interface with different teams and prioritize work based on project needs.
Email id: jobs@firstpass-semi.com
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